module counter # (parameter N=2)(load, enable, clk, out);
    input load;
    input clk;
    input enable;
    output reg [N-1:0] out;
    always @ (posedge clk or posedge load)
    begin
        if (load) out <= N*N-1;
        else if (enable) out <= out-1;
    end
endmodule

